Integrated digital circuits comprising logic circuit portions which are able to take one of at least two different logic states are well known from the state of the art, e.g. in form of conventional static complementary metal-oxide semiconductor (SCMOS) circuits. The status of such a logic circuit portion can be represented for example by flip-flops and latches realized by means of CMOS transistors.
For illustration, FIG. 1 shows a conventional CMOS latch, which is part of a digital circuit and which is able to take one of two different logic states.
The CMOS latch of FIG. 1 comprises two p-channel enhancement MOSFETs (metal-oxide semiconductor field-effect transistors) T11, T13 and two n-channel enhancement MOSFETs T12, T14. The source of the first p-channel MOSFET T11 is connected to a power supply Vdd. The drain of the first p-channel MOSFET T11 is connected to the drain of the first n-channel MOSFET T12. The source of the first n-channel MOSFET T12 is connected to ground Gnd. The second p-channel MOSFET T13 and the second n-channel MOSFET T14 are arranged in exactly the same way between the power supply Vdd and ground Gnd. The gate of the first p-channel MOSFET T11 and the gate of the first n-channel MOSFET T12 are connected on the one hand to a clocked input “in” and on the other hand to the connection between the second p-channel MOSFET T13 and the second n-channel MOSFET T14. The clocking is represented in FIG. 1 by a switch clk. The connection between the first p-channel MOSFET T11 and the first n-channel MOSFET T12 is connected on the one hand to an output “out” of the CMOS latch and on the other hand to the gate of the second p-channel MOSFET T13 and the gate of the second n-channel MOSFET T14.
When a low input voltage is provided to the input “in” of the CMOS latch, the first p-channel MOSFET T11 is conducting while the first n-channel MOSFET T12 is blocking. As a result, the output voltage at the output “out” is high, which high output voltage represents a first status of the logic circuit portion. When a high input voltage is provided to the input “in” of the CMOS latch, the first n-channel MOSFET T12 is conductive and the first p-channel MOSFET T11 is blocking. As a result, the output voltage at the output “out” is low, which low output voltage represents a second status of the logic circuit portion. The input signal is clocked in order to enable a synchronous operation of the digital circuit. As long as power is supplied by power source Vdd to the CMOS latch, the second p-channel MOSFET T13 and the second n-channel MOSFET T14 keep up the current status of the CMOS latch, until a new input voltage is provided.
All digital circuit technologies which are known today are volatile, which means that the states of the circuit are lost when the power supply is switched off completely.
In classical applications, three operation modes are therefore provided for digital circuits, namely running, stand-by and off.
In the off mode, the power is switched off completely. When proceeding from the off mode, the circuit has to go through an initialization phase, a so called boot procedure, after the power has been switched on, in order to reach a state in the running mode from which the circuit can start to work. This boot procedure requires time and power.
In the stand-by mode, the power is not switched off completely, possibly not even for inactive parts. The stand-by mode is provided in order to preserve the latest states of the digital circuit, when a device comprising the circuit is not used actively for some time.
It is a disadvantage of the stand-by mode that the transition from the running mode to the stand-by mode and back is a complex task, which equally requires time and power. It is moreover a disadvantage of the stand-by mode that a DC leakage current will flow, even if no clock is supplied. These leakage currents grow larger with each process technology generation because of the threshold voltage scaling. Leakage currents made up about 1% of the total power 10 years ago, when gates of 2 μm length were employed. The amount of the leakage current depends exponentially on the threshold voltage and increases with a factor of about five with each generation, as mentioned by Shekhar Borkar (Intel) in: “Design Challenges of Technology Scaling” IEEE 1999. Today, leakage reduction techniques are already needed.
Various concepts have been proposed to overcome the problems of the leakage current in the stand-by modes. All suffer from power requirement during the stand-by mode as well as from complicated enter and exit stand-by procedures.
In the area of storage, the problem is solved by making use in addition of non-volatile storage technologies, like FLASH memories. FLASH memories can be used to store the states of the entire digital circuit before shutting the power down completely. This operation is also called “suspend to FLASH”. To exit the power-down mode, the status information is reloaded from the memory into the digital circuit, e.g. into comprised flip-flops and latches. Thereafter, the digital circuit is ready for operation with the same states as before the off mode. However, also for this saving of states for an off mode significant time and power is needed. The optimal trade-off between power saving by power down time and power consumption by programming and loading the FLASH memory is difficult to find.
Moreover, none of the known approaches solves the problem of a sudden power failure. That is, in case of a sudden power failure, the current states of the digital circuit are lost.